Due to the complicated circuit topology and high switching frequency, field-programmable\ngate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time\nsimulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method,\nwhich has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However,\nthe oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this\npaper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance\nparameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource\noptimization method, in which the simulation time step, bit-length, and model precision are taken\ninto consideration, is presented when the power electronics converter is implemented in FPGA.\nFinally, the above method is validated on the topology of a three-phase inverter with LC filters.\nThe HIL simulation and practicality experiments verify the effect of FPGA resource optimization and\nthe validity of the ADC modeling method, respectively.
Loading....